This is where the chips that run AI actually get made. A logic foundry is a factory that etches transistors onto silicon at the most advanced nodes (a 'node' like 3nm or 5nm is roughly how small the smallest features are, smaller meaning faster and more power-efficient). Building these fabs costs tens of billions and takes years, so leading-edge capacity is scarce and concentrated. One company, TSMC, makes nearly every cutting-edge AI accelerator, with Samsung and Intel far behind. If their lines are full or disrupted, nothing downstream ships, no matter how much demand exists.

EDA (electronic design automation) software is the toolchain that turns a chip idea into a manufacturable layout: logic synthesis, place-and-route (deciding where each transistor and wire physically goes), timing signoff, physical verification, and emulation. No AI accelerator or custom ASIC (application-specific chip) can be designed, verified, or taped out to a foundry without it. Three Western vendors (Synopsys, Cadence, Siemens) control the full-flow tools, and the leading-edge libraries are tightly bound to TSMC's process nodes, so the whole industry funnels through a handful of suppliers and is exposed to export controls.

Not every chip in an AI system is made on the bleeding edge. Power-delivery chips, voltage regulators, sensors, RF (radio-frequency) parts, and microcontrollers are built on mature nodes (older, larger transistor sizes that are cheap and reliable). These come from specialty foundries (contract chip factories) running RF, power, and mixed-signal (combined digital-and-analog) processes. The choke point: this capacity is concentrated in a few Taiwanese, Chinese, and US fabs, much of it export-control sensitive. A server full of GPUs still stalls if the boring support chips around them are unavailable.

EMS (electronics manufacturing services) firms are the outsourced factories that assemble AI servers, racks, power supplies, and interconnects to a customer's design. They are a choke point because the build-out of an AI cluster needs vast, certified capacity to integrate GPU boards, liquid-cooling loops, and high-current power into finished systems, and only a handful of qualified contract manufacturers (mostly Taiwanese and Chinese) can do it at hyperscale. ODM/OEM means design plus build; OSAT (outsourced assembly and test) packages the chips. Requalifying a new plant takes quarters, so demand cannot easily route around them.

Before a chip is ever made, its building blocks are licensed, not bought outright. IP licensors rent out pre-designed circuit blocks (CPU, GPU, memory controllers, SerDes high-speed links) plus EDA software (electronic design automation, the tools that lay out and verify a chip). Almost every AI accelerator is built on Arm cores and routed through Synopsys or Cadence tools, so two or three firms gate what can be designed at all. This is a knowledge-and-tooling chokepoint: the designs are protected by patents and export controls, and there is no quick substitute, making it a true bottleneck upstream of the foundry.

HBM (high-bandwidth memory) is a tower of DRAM chips stacked vertically and wired straight into an AI processor, giving it the firehose of data an AI accelerator needs to stay fed. It is the single tightest choke point in AI hardware: only three firms make it at scale, the latest stacks (HBM3E, HBM4) are sold out for years, and each unit takes far more wafer space and harder packaging than ordinary memory. Because every AI GPU needs several HBM stacks, this supply directly caps how many AI chips the world can build.

NAND flash is the non-volatile memory (it keeps data when power is off) that stores the massive datasets, model weights, and checkpoints AI systems rely on, packaged into SSDs (solid-state drives) for data centers. It is a bottleneck because building a NAND fab (fabrication plant) costs tens of billions and takes years, so only a handful of integrated makers control nearly all global capacity. When AI demand surges, supply cannot ramp quickly, prices spike, and everything downstream waits. A second tier of fabless designers and module packagers depends entirely on these few fab owners for raw chips.

DRAM (dynamic random-access memory — the fast working memory that holds data an AI chip is actively using) is one of the tightest choke points in the AI build-out. Just three integrated device manufacturers, firms that own their own fabs, make almost all of it: Samsung, SK Hynix and Micron. The same lines produce HBM (high-bandwidth memory — DRAM dies stacked and bonded right next to a GPU), and every HBM wafer cannibalises standard DRAM supply. Building a new fab takes years and billions, so when AI demand spikes, prices surge and everything downstream waits.

An ABF substrate (Ajinomoto Build-up Film) is the finely-wired insulating base layer an AI processor sits on, fanning thousands of connections out to the circuit board. Top AI chips use FC-BGA (flip-chip ball grid array, where the chip is flipped face-down and joined to the substrate by solder bumps), the largest and hardest type to make. Only a handful of firms can build leading-edge substrates, and the raw build-up film comes from essentially one supplier, Ajinomoto. That few-supplier structure is the choke point: no substrate, no finished package, no shipped chip.

Modern AI accelerators are no longer one chip but several dies stitched together side-by-side (2.5D) or stacked (3D) on a silicon interposer (a tiny wiring board that links chips far faster than a normal circuit board). This advanced-packaging step, plus the high-end FC-BGA substrate (flip-chip ball grid array, the rigid base the chip sits and routes power through), is a choke point: only a handful of OSAT firms (outsourced assembly and test houses that package chips for others), substrate makers, and a few tool vendors like Disco and BESI can do it at AI volumes, so capacity here gates how many GPUs ship.

An AI server is built around a printed circuit board (PCB) - the flat fiberglass card that wires every chip together. AI boards need 20-plus stacked copper layers and ultra-clean 'low-loss' materials so signals running at 100-plus gigabits per second don't smear. Few plants worldwide can drill, plate, and align that many layers at high yield, and they share a thin supply of specialty resin and ultra-thin copper foil. The same makers also build IC substrates - the tiny carrier the chip itself solders onto. Capacity is booked years out, so this layer gates how fast finished servers and switches can ship.

Once a chip is fabricated, it still has to be cut, stacked, bonded and placed onto a package before it can ship. Advanced packaging is how multiple chips (logic plus stacks of memory) are fused into one module, and AI accelerators depend on it. The choke point is hybrid bonding and stacking gear (machines that join two wafers with copper-to-copper contacts so fine no solder is used) plus the dicing, grinding and inspection tools around it. A handful of suppliers like ASML, Disco, BESI and Hanmi dominate specific steps, so when their lines are full, packaging output for the whole AI industry stalls.

OSAT (Outsourced Semiconductor Assembly and Test) firms take finished silicon wafers, cut them into chips, package those chips, and test that they work. For AI accelerators this layer is a choke point because it now includes advanced packaging - chiplets, stacked memory, and bonding multiple dies into one module - where capacity is scarce and only a handful of players can do it at volume. A small set of mostly Taiwanese, Chinese, and Korean providers gates how many AI chips actually ship, so demand cannot easily route around them. Many also sit inside US-China export-control crossfire.

Every AI chip sits on a package substrate — a tiny multi-layer circuit board (the high-end type is FC-BGA, flip-chip ball grid array) that wires the silicon out to the motherboard. Interposers (a thin glass or silicon bridge) then knit the chip to its stacked memory. These parts are a choke point: only a handful of Japanese, Korean and Taiwanese firms can make the finest-line substrates, and one company (Ajinomoto) makes the insulating film (ABF) that nearly all of them use. Demand routes around nothing here, so when substrate or interposer capacity is tight, finished accelerators simply cannot ship.

After a chip is made it must be wired up and mounted, and that final step depends on a thin slice of specialist materials with very few suppliers. Ibiden, Unimicron and Ajinomoto dominate FC-BGA substrates and ABF film (FC-BGA = flip-chip ball grid array, the high-end circuit board an AI processor sits on; ABF = the insulating build-up film between its copper layers). A handful of Japanese, Taiwanese and Korean firms also control bonding wire, solder bumps and underfill (the resin that seals a chip to its substrate). Capacity is hard to add, so these names gate everything downstream.

Etch tools carve the patterns into a wafer by chemically eating away material the lithography step has masked off. Dry/plasma etch and high-aspect-ratio etch (cutting deep, narrow holes for 3D NAND memory stacks and through-silicon vias that wire stacked chips together) are gating steps for advanced logic and the memory AI chips depend on. The high-end market is dominated by a handful of suppliers, mainly Lam Research, Applied Materials and Tokyo Electron, so etch capacity and tool lead times directly cap how fast new fabs can ramp. Export controls add another choke point on who can buy the most advanced tools.

Lithography is the step that prints circuit patterns onto silicon wafers using light, and it is the tightest choke point in chipmaking. The most advanced patterning, EUV (extreme ultraviolet lithography, which uses very short-wavelength light to draw the smallest features on AI chips), is built by exactly one company on Earth, ASML. The next tier down, DUV (deep ultraviolet, the older long-wavelength tool for less fine features), plus the metrology and inspection gear that checks each layer, comes from a handful of Japanese, US and Chinese firms. No competing fab can route around these few suppliers, and the machines also sit at the center of US-China export controls, so supply gates everything downstream.

Deposition is how a chip gets built up layer by layer: machines lay down ultra-thin films of metal and insulator onto the silicon wafer. The main methods are CVD (chemical vapor deposition, where gases react to coat the surface), PVD or sputtering (physically blasting atoms off a target onto the wafer), ALD (atomic layer deposition, building films one atomic layer at a time for precision), and epitaxy (growing crystal layers). These films make the wiring, barriers, and gate insulators that advanced AI chips and HBM (high-bandwidth memory) stacks depend on. A handful of suppliers dominate the most demanding tools, so capacity here gates everything downstream.

Before a chip is ever etched, someone has to physically build the fab — the ultra-clean factory it is made in. This layer is the EPC (engineering, procurement and construction) firms, cleanroom specialists and fab-automation builders that pour the concrete, install vibration-free floors, and fit out cleanrooms (sealed rooms with filtered air where a speck of dust ruins a wafer). It is a bottleneck because only a handful of firms worldwide can build a leading-edge fab on schedule, and each one takes years; if they are booked, new AI-chip capacity simply cannot come online, no matter the demand downstream.

After an AI chip is built, every unit must be tested and stress-screened before it ships, or defects reach data centers. This layer makes the gear that does it: ATE (automated test equipment, the machines that run electrical checks on each chip), handlers and sockets that grip the device under test, burn-in systems that bake chips at high heat and voltage to weed out early failures, and probe cards (beds of fine needles that touch a wafer to test chips before they are diced). Two firms, Advantest and Teradyne, dominate high-end ATE, and a handful of Japanese and Korean specialists supply the precision sockets, probes, and burn-in ovens. Few qualified suppliers and long lead times make this a quiet choke point: testing capacity gates how fast finished AI silicon can be certified and shipped.

Metrology and inspection tools are the chip industry's quality-control eyes: machines that measure features and hunt defects on a wafer (the silicon disk chips are printed on). They cover CD-SEM (a scanning electron microscope that gauges line widths a few nanometres wide), overlay metrology (checking that stacked print layers line up), film-thickness measurement, and optical and e-beam defect inspection. As AI chips push to the most advanced nodes, the tolerance for flaws shrinks, so without these tools fabs cannot keep yield (the share of good chips per wafer) high. A handful of firms, led by KLA, dominate, making this a narrow choke point.

Every chip starts as a polished silicon wafer (a thin, ultra-pure disc of single-crystal silicon that transistors are etched onto). The hardest grades to make are prime, epitaxial (a fresh defect-free silicon layer grown on top), and SOI (silicon-on-insulator, silicon stacked over an insulating layer to cut leakage and speed switching). This is a chokepoint because only a handful of suppliers worldwide can grow crystals flat and pure enough for leading-edge logic and memory, capacity expansion takes years, and most of it sits in Japan, Taiwan, Korea and Germany. No wafers, no chips downstream.

Photolithography prints circuit patterns onto silicon by shining light through a photomask (a quartz-and-chrome stencil) onto a light-sensitive coating called photoresist. For the leading-edge chips that AI accelerators need, that light is EUV — extreme ultraviolet, a very short wavelength that demands new resist chemistry few firms can make. The supply is concentrated: a handful of Japanese and Korean specialty-chemical houses dominate EUV resists, developers, anti-reflective coatings, and EUV pellicles (thin protective membranes over the mask). With so few qualified suppliers and slow, finicky qualification, this layer gates how many advanced chips a fab can produce.

Chips are not just etched silicon; they are built with ultra-high-purity gases and wet chemicals at every step. Bulk gases (nitrogen, argon, hydrogen) flood the fab, while specialty gases like silane and NF3 (nitrogen trifluoride, used to clean deposition chambers) and ultra-pure acids and solvents do the actual deposition, etch, and cleaning. Purity must reach parts-per-billion, so only a handful of qualified suppliers exist per molecule, and switching vendors can take a year of re-qualification. That tight, geographically concentrated supplier base makes this layer a choke point: starve it and every fab downstream stalls.

Every chip is built up in dozens of metal and insulator layers, and between each layer the wafer surface must be made atomically flat. That smoothing step is CMP (chemical-mechanical planarization), which scrubs the wafer using a liquid abrasive called slurry against a polishing pad, then cleans off the residue. Slurries are tuned per material (oxide, copper, tungsten, barrier) and qualifying a new one inside a fab takes years, so customers rarely switch suppliers. A handful of Japanese, Korean, and US chemical makers dominate the high-end formulas, making this a quiet but hard chokepoint: no clean planarized wafer, no working AI chip downstream.

Rare earths are 17 metals (notably neodymium, praseodymium, dysprosium, terbium) that make the permanent magnets inside AI data-center cooling fans, hard drives, robotics actuators, and the motors of the power equipment feeding compute. The chokepoint is not the ore but the separation and refining step that splits the chemically near-identical elements apart, plus turning oxides into metal and magnets. China controls roughly 85-90% of that midstream refining and almost all heavy-rare-earth processing, so export licenses can gate the entire chain. Western miners can dig ore, but very few can separate or refine it, leaving demand unable to route around the bottleneck.

Big AI data centers need huge banks of batteries for backup power and grid storage, and those batteries depend on a handful of mined-and-refined metals: lithium, nickel, cobalt, manganese, and graphite (the anode material, the negative electrode where charge is stored). The chokepoint is not the digging but the refining: China processes the majority of the world's lithium, cobalt, and graphite, so even ore mined elsewhere flows through a few Chinese converters. Mines take roughly a decade to permit and build, and export controls can throttle supply, so downstream cell and pack makers cannot easily route around these few suppliers.

Chips are built from trace elements most people never hear of: gallium and germanium for high-speed and infrared optics, tantalum for capacitors, tungsten for interconnects, antimony for chip dopants, plus cobalt, indium, palladium and ultra-high-purity quartz for crucibles. Supply is the chokepoint: China refines the bulk of gallium, germanium, tungsten and antimony, and has shown it will use export licences as leverage. These metals are by-products of zinc, copper and coal mining, so output cannot scale on demand. A handful of refiners outside China gate everything downstream.

AI servers need copper, nickel, cobalt, lithium and precious metals like gold and platinum-group metals (PGMs, the rare catalyst metals). Mining alone cannot meet demand fast enough, so recovering these from electronic waste, spent batteries, used catalysts and industrial scrap (urban mining, treating discarded goods as an ore body) is now a parallel supply source. The choke point is refining: only a handful of smelters and hydrometallurgical plants (chemical processes that dissolve scrap to extract pure metal) can turn mixed waste back into chip-grade material, and that capacity sits with a small set of Asian and European players.

Networking silicon is the set of chips that move data between AI accelerators inside a cluster: switch ASICs (the chip that routes traffic across a fabric), NICs and DPUs (network interface and data-processing units that connect a server to the network), plus the SerDes and retimers (circuits that push signals fast and clean over copper or fiber). As models scale, the GPUs sit idle unless data reaches them fast enough, so the bottleneck shifts from compute to interconnect. A handful of suppliers gate high-radix switching and high-speed connectivity, with the merchant market concentrated and export controls adding fragility.

Physical AI - robots, self-driving cars, drones - can only act on what it can sense, so the chain runs through a thin layer of specialist sensor makers. Image sensors (CIS - CMOS image sensors, the light-detecting chips behind every camera) are dominated by Sony, with Samsung and a few Chinese fabs behind it. Lidar (laser range-finding that builds a 3D map by timing reflected light) and automotive radar add more single-source choke points. Few firms can build automotive-grade sensors at scale and pass safety qualification, so demand cannot simply route around them.

AI clusters move enormous amounts of data between thousands of GPUs, so they are wired together with optical fiber and high-speed copper. The choke points are optical transceivers (modules that turn electrical signals into laser light and back, letting data travel over fiber at 800G/1.6T speeds) and the precision connectors and DAC/AOC cables (direct-attach copper and active optical cables that link racks). A handful of vendors, heavily concentrated in China, Taiwan and Japan, dominate transceiver and connector supply, while a few firms control the glass and fiber draw. When AI demand spikes, lead times and laser-chip capacity here gate how fast clusters can be built.

AI clusters are only as fast as the wires between their chips. Switches (boxes that route data between servers) and NICs (network interface cards, the ports that plug a server into the network) plus DPUs (data processing units, NICs with their own onboard compute) must move trillions of bits per second or the GPUs sit idle waiting for data. The bottleneck is concentration: a handful of merchant-silicon designers (Broadcom, Nvidia, Marvell) supply the switch and NIC chips, a few Taiwanese ODMs assemble the boxes, and Nvidia's proprietary fabric locks in many buyers. Few suppliers gate the whole rack.

Optical transceivers are the plug-in modules that turn an AI chip's electrical signals into laser light so racks of GPUs can talk to each other over fiber at 800 gigabits and 1.6 terabits per second. As clusters scale to tens of thousands of accelerators, the number of optical links explodes faster than chip count. The choke point is narrow: a handful of vendors (many in China and Taiwan) plus scarce inputs (lasers, modulators, silicon photonics) gate output. The newest speeds rely on PAM4 (a signaling scheme squeezing more bits per pulse) and co-packaged optics, both supply-constrained, so the whole fabric stalls if modules are short.

Co-packaged optics (CPO) moves the light-based data link right next to the chip, fusing the optical engine that turns electrical signals into laser light onto the same package as an AI accelerator or switch ASIC (application-specific integrated circuit, a custom switching chip). This shaves power and lets data centers push far more bandwidth per port. The choke point is silicon photonics — etching optical components into silicon — plus the precise lasers, advanced packaging, and substrates needed to bond optics to chips. Very few firms can do this at volume, so a handful of foundries, optical-engine makers, and packaging houses gate everything downstream.

An AI server is only as fast as the wires between its chips. This layer makes the high-speed connectors, backplanes (the boards that link cards inside a rack), copper cables, and fiber that carry signals between GPUs, switches, and racks. As data rates climb to 224G (224 gigabits per second per lane), the physical interconnect becomes a choke point: only a few firms can build connectors and active cables that hold a clean signal at those speeds. Tight tooling capacity and qualified-supplier lists mean GPU clusters cannot scale faster than these parts ship.

AI data centers need vast, steady electricity, but the grid often cannot connect new sites fast enough. This layer covers on-site power that bypasses that wait: fuel cells (devices that turn hydrogen or natural gas straight into electricity through a chemical reaction, no combustion), gas turbines, small modular reactors, and the backup gear that keeps racks alive during outages. It is a bottleneck because few firms can ship grid-scale fuel cells or qualified backup power at volume, and lead times for turbines and reactors stretch years, gating how quickly compute can come online.

AI data centers need vast, reliable electricity faster than the grid can deliver it, so operators increasingly build dedicated on-site power: gas turbines (engines that spin generators by burning natural gas), reciprocating gas engines (piston engines like oversized car engines), and fuel cells (devices that turn gas into electricity chemically without burning it). Only a handful of firms worldwide can forge the large heavy-duty turbines, and order books now stretch years out. That scarce manufacturing capacity gates how quickly new compute can come online, making this layer a hard physical chokepoint downstream of every chip.

Every AI server rack runs on DC power converted from the building's AC mains by a PSU (power supply unit, the brick that turns wall current into the low, stable voltage chips need) and fed through a power shelf (a shared tray of redundant PSUs serving a whole rack). As rack power climbs from a few kilowatts toward 100kW-plus, only a handful of vendors can build PSUs efficient and dense enough to keep up. Capacity, high-efficiency designs, and qualified suppliers are scarce, so this layer gates how fast AI racks can actually be powered and deployed.

AI servers draw far more electricity than ordinary computers, and that power must be stepped down and cleaned up by power chips before it reaches the GPUs. These are the IGBTs, MOSFETs, and newer SiC and GaN devices (IGBT = a high-power switch; MOSFET = a fast voltage switch; SiC = silicon carbide and GaN = gallium nitride, materials that switch faster and run cooler than plain silicon) inside the power supplies, rectifiers, and voltage regulators feeding every rack. A handful of integrated makers (IDMs, firms that both design and fabricate their own chips) dominate the high-efficiency end, so when AI demand spikes, power-chip capacity becomes a choke point that throttles how many servers can actually be energised.

Every AI rack now draws 40-100kW or more, and that power has to be carried, split, and metered before it reaches a single GPU. This layer covers the gear that does it: rack PDUs (power distribution units that fan grid power out to individual servers and meter each outlet), busways (overhead bars that drop power anywhere along a row), switchgear (the breakers and disconnects that protect and isolate circuits), and UPS (uninterruptible power supplies that ride through outages). A handful of incumbents hold the certifications, copper supply, and multi-year order books, so lead times stretch and capacity gates how fast new data centers energize.

AI servers pack racks that draw 50-130+ kilowatts of power, far beyond what fans and chilled air alone can remove, so heat removal has become a hard limit on how dense you can build. Operators need CRAC/CRAH units (computer-room air conditioners/handlers that cool the room), CDUs (coolant distribution units that pump liquid to the chips), direct-to-chip cold plates, and rear-door heat exchangers. Few vendors can supply these at scale with the quality and lead times hyperscalers demand, and specialty coolant fluids add another scarce input. When cooling slips, the GPUs cannot be switched on, making this layer a genuine choke point.

This is the mechanical skeleton AI servers live in: the racks (steel cabinets that hold the servers), chassis (the metal box around each server), slide rails, cable management, and hot/cold aisle containment that organize airflow. As GPU racks jump from a few kilowatts to 40kW+ each, the metalwork has to be re-engineered for liquid cooling and far heavier loads, and a handful of Taiwanese and Chinese specialists (slide rails, enclosures, integration) make most of it. When that capacity is booked out, hyperscalers cannot deploy chips no matter how many they buy, so this unglamorous layer quietly gates the whole build-out.

AI data centers draw enormous, spiky power loads, so they need UPS (uninterruptible power supply - battery-and-electronics gear that keeps servers running through grid dips and switches to backup without a flicker) plus large battery banks to shave demand peaks. The chokepoint is twofold: a handful of firms make the high-power UPS, switchgear and power electronics that condition and route the electricity, and battery cells come mostly from a concentrated set of Asian makers. Backup generators, fuel cells and grid-scale storage add further single-source pinch points, so scarce capacity here gates how fast new compute can come online.

Before an AI data center can draw power, the electricity has to reach it through high-voltage transmission lines, substations, and switchgear (the heavy-duty switches and circuit breakers that route and protect power flow). The chokepoint is hardware: large power transformers (the units that step voltage up or down) now carry multi-year order backlogs, and only a handful of firms build the biggest ones. Add scarce high-voltage cable, skilled grid-construction crews, and slow interconnection permitting, and the grid becomes the gate that decides how fast new compute can actually switch on.

Hyperscalers (the largest cloud and AI operators like the big data-center builders) sign PPAs — power purchase agreements, long-term contracts to buy electricity at a fixed price — to lock in the huge, round-the-clock power an AI data center needs. The bottleneck is supply: only a handful of utility-scale developers and IPPs (independent power producers, companies that build and sell generation without owning the retail grid) can deliver gigawatts of firm renewable or nuclear capacity on a usable timeline. Permitting, grid connection queues, and scarce new build mean compute capacity is increasingly gated by who can contract clean power, not by chips.

AI data centers need vast, around-the-clock electricity, and nuclear is the cleanest dense source that runs 24/7. The choke point is not desire but capacity: enriched uranium fuel comes from a handful of suppliers (Russia, Kazakhstan, plus a few Western enrichers), and only a few firms can forge reactor-grade pressure vessels or build a new plant. SMRs (small modular reactors, factory-built mini-reactors) are mostly still pre-revenue. Because new reactors take years to license and build, and fuel and heavy forgings have thin supply, power becomes the gating constraint on bringing compute online.

AI data centers now demand 100MW+ hookups to the utility grid, and that power can't flow without big iron in the middle: large power transformers (which step voltage up or down so electricity can travel and then be safely used), switchgear (the breakers and switches that route and protect circuits), and substations (the fenced yards where all this lives). Grain-oriented electrical steel, bushings, and skilled winding labor are scarce, and a single large transformer can take two to four years to deliver. A handful of makers across Korea, Japan, China, the US and Europe gate every new site, so this layer throttles how fast compute can actually be plugged in.

Self-driving vehicles are gated by a handful of chokepoints: the AI compute brain that runs the driving software (the ADAS/autonomy SoC — a single chip combining processor, AI accelerator and sensors-input, made by very few firms), and the sensing layer led by LiDAR (light detection and ranging, lasers that build a 3D map of the road). Both need scarce automotive-grade silicon and validated software stacks that take years to qualify, so demand cannot easily route around the few suppliers. A stumble at any one — chip, sensor, or full self-driving stack — stalls every carmaker and robotaxi downstream.

Humanoid robots and embodied AI (AI that controls a physical body, not just a screen) hinge on a handful of scarce mechanical parts. Each robot needs dozens of precision actuators built around harmonic-drive and planetary gearboxes (compact gears that shrink fast motor spins into slow, high-force joint motion) plus ball screws and roller bearings, all made to micron tolerances by a few Japanese, Taiwanese, Chinese and German specialists. Add force/torque sensors, machine-vision and LiDAR perception, and onboard AI compute chips. Because so few firms can mass-produce these gears and actuators cheaply, they gate how fast humanoids can scale.

AI factories and the chip fabs that feed them cannot be built or run without machines that physically move things: industrial robot arms that assemble servers, AMHS (automated material handling systems, the overhead rail and robots that ferry wafers around a fab without human touch), and the precision parts inside every robot. The choke point is concentration. A handful of Japanese firms dominate the high-precision gearing (harmonic and cycloidal reducers) and servo motors every robot needs, while a few names control fab wafer-handling and metrology. Few suppliers, long lead times, and deep know-how mean downstream demand cannot easily route around them.